CS207 Digital Logic

Spring 2019

Instructor

Dr. James Yu 余剑峤

Course Description

Digital logic is the representation of signals and sequences of a digital circuit through numbers. It is the basis for digital computing and provides a fundamental understanding on how circuits and hardware communicate within a computer. Digital logic is typically embedded into most electronic devices, including calculators, computers, video games, and watches. This field is utilized by many careers that work with computers and technology. This is a foundational course in digital design that aims to provide an understanding of the fundamental concepts, circuits in digital design, and expose students to the mainstream approaches and technologies used in digital design. This course allows students to gain hands-on experience by building computer hardware through the use of algorithms and simple inputs. They learn how simple inputs of ones and zeros can be used to store information on computers, including documents, images, sounds, and movies. On successful completion of this course,students should be able to demonstrate an in-depth knowledge of the fundamental concepts and issues and the engineering principles involved in digital design and be able to design a series of combinational and sequential circuits. In addition, they should demonstrate through hands-on experimentation knowledge of the digital design process using HDLs.

Logistics

Course Materials

There is no required text for this course. A reference textbook is “Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog“ by M. Morri et al. Lecture notes and lab sheets will be posted periodically on this page.

Coursework

There will be three written assignments and a final examination. The assignments will contain written questions and lab reports. We try very hard to make questions unambiguous, but some ambiguities may remain. Ask if confused or state your assumptions explicitly. Reasonable assumptions will be accepted in case of ambiguous questions.

Grade Breakdown

This is set by the university, and no adjustments can be made.

Schedule and Syllabus

Unless otherwise specified the lectures are Monday 8:00am to 9:50am at Room 405 of Teaching Building No. 1, SUSTech. The lab sessions are Monday 10:20am to 12:10pm at Room 201 of Teaching Building No. 2, SUSTech.

EventDateDescriptionMaterials
Week #1Monday, Feb. 18Course Introduction and Binary Numbers
Course overview and logistics
Binary, octal, hexadecimal numbers
Binary codes and basic binary logic
[slides]
[lab sheets]
Week #2Monday, Feb. 25Boolean Algebra and Logic Gates
Boolean function
Canonical and standard form function
Digital logic gates
[slides]
[lab sheets]
Week #3Monday, Mar. 4Gate‐Level Minimization - Part 1
The Karnauph map simplification method
Three- and four-variable K-map
Prime implicants and don’t care condition
[slides]
[lab sheets]
[lab source code]
Week #4Monday, Mar. 11Gate‐Level Minimization - Part 2
NAND and NOR implementation
Other two-level logic function implementation
XOR function implementation
[lab sheets]
Week #5Monday, Mar. 18Combinational Logic - Part 1
Combinational circuit
Analyze and design a combinational circuit
Half adder and full adder
[slides]
[lab sheets]
DeadlineFriday, Mar. 22Assignment #1 Due[questions]
Week #6Monday, Mar. 25Combinational Logic - Part 2
Binary adder and subtractor
Overflow and decimal adder
Binary multiplier and magnitude comparator
[lab sheets]
Week #7Monday, Apr. 1Combinational Logic - Part 3
Decoder and encoder
Combinational logic implementation
Multiplexer
[lab sheets]
Week #8Monday, Apr. 8Synchronous Sequential Logic - Part 1
Week #9Monday, Apr. 15Synchronous Sequential Logic - Part 2
DeadlineFriday, Apr. 19Assignment #2 Due
Week #10Monday, Apr. 22Registers and Counters - Part 1
Week #11Monday, Apr. 29Registers and Counters - Part 2
Week #12Monday, May 6Memory and Programmable Logic - Part 1
Week #13Monday, May 13Memory and Programmable Logic - Part 2
DeadlineFriday, May 17Assignment #3 Due
Week #14Monday, May 20Register Transfer Level Design - Part 1
Week #15Monday, May 27Register Transfer Level Design - Part 2