Digital logic is the representation of signals and sequences of a digital circuit through numbers. It is the basis for digital computing and provides a fundamental understanding on how circuits and hardware communicate within a computer. Digital logic is typically embedded into most electronic devices, including calculators, computers, video games, and watches. This field is utilized by many careers that work with computers and technology. This is a foundational course in digital design that aims to provide an understanding of the fundamental concepts, circuits in digital design, and expose students to the mainstream approaches and technologies used in digital design. This course allows students to gain hands-on experience by building computer hardware through the use of algorithms and simple inputs. They learn how simple inputs of ones and zeros can be used to store information on computers, including documents, images, sounds, and movies. On successful completion of this course,students should be able to demonstrate an in-depth knowledge of the fundamental concepts and issues and the engineering principles involved in digital design and be able to design a series of combinational and sequential circuits. In addition, they should demonstrate through hands-on experimentation knowledge of the digital design process using HDLs.
There is no required text for this course. A reference textbook is “Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog“ by M. Morris Mano et al. Lecture notes and lab sheets will be posted periodically on this page.
There will be three written assignments and a final examination. The assignments will contain written questions and lab reports. We try very hard to make questions unambiguous, but some ambiguities may remain. Ask if confused or state your assumptions explicitly. Reasonable assumptions will be accepted in case of ambiguous questions.
This is set by the university, and no adjustments can be made.
Unless otherwise specified the lectures are Monday 8:00am to 9:50am at Room 405 of Teaching Building No. 1, SUSTech. The lab sessions are Monday 10:20am to 12:10pm at Room 201 of Teaching Building No. 2, SUSTech.
| Event | Date | Description | Materials |
|---|---|---|---|
| Week #1 | Monday, Feb. 18 | Course Introduction and Binary Numbers Course overview and logistics Binary, octal, hexadecimal numbers Binary codes and basic binary logic |
[slides] [lab sheets] |
| Week #2 | Monday, Feb. 25 | Boolean Algebra and Logic Gates Boolean function Canonical and standard form function Digital logic gates |
[slides] [lab sheets] |
| Week #3 | Monday, Mar. 4 | Gate‐Level Minimization - Part 1 The Karnauph map simplification method Three- and four-variable K-map Prime implicants and don’t care condition |
[slides] [lab sheets] [lab source code] |
| Week #4 | Monday, Mar. 11 | Gate‐Level Minimization - Part 2 NAND and NOR implementation Other two-level logic function implementation XOR function implementation |
[lab sheets] |
| Week #5 | Monday, Mar. 18 | Combinational Logic - Part 1 Combinational circuit Analyze and design a combinational circuit Half adder and full adder |
[slides] [lab sheets] |
| Deadline | Friday, Mar. 22 | Assignment #1 Due Questions on Digital Logic theories Lab experiment results |
[questions] [solutions] [submit via Sakai] |
| Week #6 | Monday, Mar. 25 | Combinational Logic - Part 2 Binary adder and subtractor Overflow and decimal adder Binary multiplier and magnitude comparator |
[lab sheets] [lab source code] |
| Week #7 | Monday, Apr. 1 | Combinational Logic - Part 3 Decoder and encoder Combinational logic implementation Multiplexer |
[lab sheets] [lab source code] |
| Week #8 | Monday, Apr. 8 | Synchronous Sequential Logic - Part 1 Sequential circuits Latches and flip-flops Analysis of clocked sequential circuits |
[slides] [lab sheets] [lab source code] |
| Week #9 | Monday, Apr. 15 | Synchronous Sequential Logic - Part 2 State reduction and assignment Sequential circuit design prodecure |
[lab sheets] [lab source code] |
| Deadline | Tuesday, Apr. 23 |
Assignment #2 Due Questions on Digital Logic theories Lab experiment results |
[questions] [submit via Sakai] |
| Week #10 | Monday, Apr. 22 | Registers and Counters - Part 1 Registers Shift registers |
[slides] [lab sheets] [lab source code] |
| Week #11 | Monday, Apr. 29 | Registers and Counters - Part 2 Ripple counters Synchronous counters |
[lab sheets] [lab source code] |
| Week #12 | Monday, May 6 | Memory and Programmable Logic - Part 1 Random-access memory Memory decoding Error detection and correction |
[slides] [mini-project] |
| Week #13 | Monday, May 13 | Memory and Programmable Logic - Part 2 Read-only memory Programmable logic array Programmable array logic |
|
| Deadline | Friday, May 31 |
Assignment #3 Due Questions on Digital Logic theories Lab experiment results |
[questions] [submit via Sakai] |
| Week #14 | Monday, May 20 | Quiz and Review | |
| Week #15 | Monday, May 27 | Review |